Karl-Tasso Knoepfle, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg)
Martin Feuerstack-Raible (University of Heidelberg)
Niels van Bakel, Jo van den Brand (Free University of Amsterdam)
Neville Harnew, Nigel Smale (University of Oxford)
!!
For the LHCb experiment at CERN a dedicated readout chip is under development. 
This so-called Beetle chip has to be able to read out the Silicon Micro Strip 
detector, the RICH counters and the Inner Tracker.
As a first step, two prototype chips have been designed and manufactured in a
standard 0.25um CMOS technology, since results from the RD49 group show 
minimum threshold voltage shift for deep submicron processes after irradiation.
Special layout techniques, like enclosed transistors and guardrings, have been
used to further improve the behaviour under irradiation with respect to leakage
current and single event latchup.
One chip contains 3 different sets of frontend amplifier circuits. They have
been optimized for the LHCb requirements with respect to peaking time, fall
time, noise and power consumption. Simulation results show a peaking and fall
time of both 25ns at a power consumption of 1.8mW. These circuits have a dynamic
range from -10MIP to +10MIP (1MIP=11.000 electrons). The bias generator chip
contains 2 voltage DACs with a resolution of 10bit within the power supply. The
power consumption has been simulated to be 200uW for each DAC. It also contains
8 current DACs, that can be adjusted between 0.63uA and 640uA with a resolution
of 10bit. The power consumption of one current DAC is simulated to be 1.3mW as a
maximum value. Three different current sources have been designed, all with a
nominal output current of 100uA. The simulated change on the output current is
less than 1% up to 0.5V of the power supply voltage. 
A printed circuit board has been designed to integrate both test chips and
characterize the performance of the chips individually and as a system. It is
designed such that it can be mounted on a dedicated detector and read it out.
The test results will be presented and compared with the simulations.
Explanations for discrepancies will be given where possible, and plans for
future submissions will be presented.
Teststructures were irradiated up to a total dose of 10 Mrad. They consisted of
linear minimum size transistors and edgeless and linear transistors with a W/L 
of 6.8/0.7 of both n- and p-type with guardrings, as well as an edgeless transistor with a very
large W/L, as used in the frontend amplifier. Parameters tested were the 
leakage current, the threshold voltage and the gain factor.

!!
For the LHCb experiment a dedicated 128 channel analogue pipeline chip, named
Beetle, is under development. This readout chip will be made in a standard
0.25um CMOS process.
Two prototype chips have been developed. One of them includes different types 
of
a frontend amplifier, whereas the other chip contains bias generators and
current sources. 
The basic design of the frontend amplifier and bias generator chip is 
explained.
!!