Carlos Beltran Almeida, INESC/IST
Joao Paulo Teixeira, INESC/IST
Isabel Cacho Teixeira, INESC/IST
Nuno Cardoso, INESC
Marcelino Santos, INESC/IST
Jose Augusto, INESC/IST
Joao Varela, CERN/LIP
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The CMS ECAL upper-level readout and trigger system is composed of 
about one thousand boards installed in sixty 9-U VME crates. The 
complexity of the design and implementation of such a system requires 
the use of Design for Testability techniques, in order to achieve a 
testable system during all the phases of the product lifetime.

During the first year of the collaboration, INESC has been evaluating
the use of the ANSI IEEE 1149.1 Standard at different modeling levels
(component, MCM, board, system), the inclusion of self-test techniques
and in-system test procedures, as well as, the specification of the
system using a high level description approach. This study suggests 
the implementation of the IEEE 1149.1 at system level, using an 
appropriated integrated circuit to interface the system at their
different levels.

The introduction of BIST in system components, namely ASICs, is being
studied, especially for the synchronisation IC, under development by
TECMIC.

1 - Application of Boundary Scan at System Level
The upper-level readout and trigger system is controlled, during the 
normal operation of the acquisition system, by a controller board 
housed in each crate. The main objective of this task is to develop 
a VME based JTAG controller (hardware/software) enabling the application 
of a boundary scan test to the sub-system during the idle time or 
when a maintenance operation is required.
This task has two components:
1.1 Development of a boundary scan test module being the interface
between the sub-system controller and the VME dedicated lines to
implement the IEEE 1149.1 test bus.
1.2 Development of the software for downloading the test and for 
getting back to the controller the test results.

2 - ASIC Built-in Self-Test and Reliability
This task has two main objectives:
2.2 To develop a BIST solution for the Sync Tx/Rx ASIC, portable to a
standard-cell or gate array technology implementation, with low area
overhead, low speed degradation and low power BIST application;
2.2 To ascertain the test effectiveness of test patterns, targeting at
very low escape rates, using a Defect-Oriented (DO) test strategy, and
INESC proprietary tools. Experiments will be carried out both for the
Sync Tx/Rx IC, and other ASICs currently being developed by other
partners, namely CAEN. Moreover, DO reliability issues will be
investigated, with the aim of guiding the technology selection for the
final product.

The development of the BIST solution for the synchronisation circuit
will be carried out within the context of board and system test,
ensuring BST (Boundary Scan Test) compatibility and test reusability,
in order to shorten development times, and to increase design productivity.
Both production and lifetime testing are considered.

DO test validation, and ASIC reliability will be addressed, in the
perspective of deriving high-quality tests, capable of uncovering
physical defects, likely to occur during production or field use, and of
identifying layout-level areas associated with yield drops, and
potentially hard to detect faults. Moreover, it will be exploited the
correlation between yield killer defects, and reliability flaws.


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This contribution describes the work on testability in the CMS ECAL
upper-level readout and trigger system being carried out by the INESC in
collaboration with LIP. In particular, work on the extension of 
boundary scan test of electronic boards to system level and on
the introduction of self test in ASICs will be reviewed. This 
activity is part of a more global effort on testability and 
reliability of the upper-level readout and trigger system done 
in collaboration with CERN, Politecnico Torino and CAEN.

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