Osamu Sasaki (KEK), Mitsuhiro Yoshida (ICEPP, Tokyo) and Atlas TGC Collaboration !! The Atlas experiment in the LHC uses Thin Gap Chambers (TGC) as its forward muon trigger detectors. Forward-going muon tracks are bent by a magnetic field generated by a toroidal coil and pass through the TGCs where their momenta are measured for level-1 trigger. There will be a triplet TGC wheel followed by two wheels of TGC doublets, totaling 7 layers of TGCs per side. The total number of TGCs are 3600 and we will be dealing with TGC signals from their anodes (several wires are ganged together) and strips, totaling nearly 40k channels. Since the machine cycle of the LHC is 40MHz, the bunch identification capability is mandatory for the electronics and the detector to provide the trigger and readout processing. The capacitance of the TGC as a signal source is a few hundred pF, which is rather large capacitance when compared with that of an ordinary chamber. We have designed and built a chip containing 4 channels of amplifier- shaper-discriminators (ASDs) for the TGCs. The process we have been using is called SONY semi-custom Analog Master Slice. SONY will receive complete design of the circuit from customers and produce wafers containing various circuits for the multiple customers on the same wafer. The base-structure we used contains 850 NPN transistors, 384 PNP transistors, 1738 resistors and 42 capacitors, totaling approximately 1000 usable elements. There are five kinds of NPN transistors in the chip including low noise transistors and power transistors. The standard transistor has fT = 3.2 GHz. The low noise transistor has fT = 950 MHz and rbb' = 17.5 ohm. There also are two kinds of PNP transistors of which the standard one has fT = 300 MHz. Capacitance of capacitor elements are 2 pF and 20 pF with maximum available capacitance to be totaling 408 pF in all. Resistor elements are either 8 kohm or 2.5 kohm poli-silicon resistors and 297 ohm diffused resistors. The first section of the ASD is a charge amplifier of common-emitter cascode configuration with 16 ns integration time. The low noise NPN transistor is used for its first stage. The second section consists of a differential amplifier with a gain of 8 and a baseline restoration circuit. The comparator is composed of 3 stages of differential amplifiers. The following is the summary of the ASD IC. Process : SONY Analog Master Slice (bipolar semi-custom) Specification : pre-amplifier with a gain of 0.8 V/pC. open-emitter analog output. main-amplifier with a gain of 7. baseline restoration circuit. comparator with LVDS outputs. enc ~ 7500 electrons at Cd = 150pF. 4 channels in a 48QFP plastic package. common Vth for all 4 channels. required power : +/- 3V, GND. 59 mW/ch when driving a 100 ohm load. Irradiation test against ionization dose and neutrons has been done and it is proved that the ASD chips as well as each component transistors retain the properties for the TGC read-out after 10 years of LHC running even at the location of the worst background condition in the forward muon trigger station. A 16-ch ASD board has been designed, 200 ASD board has already build and being used in Israel and KEK. In this fall, 100K pieces of chips are to be mass-produced and then 25K of ASD boards will be assembled in this winter. !! A 4-ch ASD chip and a 16-ch ASD board were designed and built for Thin Gap Chambers in the forward muon trigger system of the LHC Atlas experiment. The ASD IC uses SONY bipolar technology. The gain of the preamplifier is 0.8V/pC and output from the preamplifier is received by the main-amplifier with a gain of 7. The baseline restoration circuit is incorporated in the main-amplifier. The IC also has analog outputs of the preamplifiers. The equivalent noise charge at input capacitance of 150 pF is around 7500 electrons. Irradiation tests against ionization dose and neutrons has been done and the IC successfully cleared the requirement. !!