Dario B. Crosetto
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This work is described in very details. The complete project is made available on the web (including the VHDL source code and the bitstream file), to allow any user to download into OR3T30 FPGA and test it on the hardware testbench. Software testbench are also provided on the web. The flexibility, modularity and scalability of this circuit has the commonality to meet the requirements of different experiments.
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The complete design of a flexible front-end module suitable for different experiments is presented. The depth/width of the FIFO, the bits that are form the trigger word to be sent to the trigger processor, the depth of the pipeline buffer, the variable delay applicable to each input bit in order to synchronize the signals from the detector, are configurable and can be adapted to the requirements of different experiments or can accommodate future changes for the same experiment. The VHDL code (written in synthesizable generic VHDL code) of the entire project suitable for implementation into ASIC is provided. The full implementation into Lucent Technologies FPGA ORCA OR3T30, including the bitstream file to be downloaded into the FPGA, is provided. 
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