Gustavo Cancelo, Fermilab
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SUMMARY
Pixels Detectors are the future for most of the inner tracker and vertex detector systems in high energy physic experiments. They provide excellent resolution. The spatial resolution depends on the pixel size and whether only digital or digital plus analog information is provided by the pixel front end amplifier and discriminator cell. 

The present work has been done at Fermilab, as part of the specification and design of a pixel device to meet BTeV experiment requirements [1]. Since BTeV plans to use the pixel detector as part of the trigger system the most important characteristic is speed. The primary goal is to achieve a readout rate close to five hits per beam crossing. 
The importance of every component block of the proposed architecture is analyzed through modeling and simulation. This analysis is of fundamental importance to understand architectural bottlenecks as well as to avoid solutions, which can be attractive, in principle, but do not make a substantial improvement to the optimal design. 

The pixel cells store hit location and time information. Time information is stored indirectly, by storing a pointer to a set of registers at the end of a pixel's column. The pixels are organized by columns, and share an End of Column Logic at the bottom. There is an Input Control Logic that may act as a lower level trigger and also receives and decodes instructions to the chip. The Output Control Logic controllers readout pixel hits into on chip buffers (FIFOs). The pixel hits are chronologically organized by time stamp, facilitating the work of the trigger processor and saving time in a very time critical job. Finally, the data is readout off chip from the buffers using a high speed synchronous communication channel. 

The column based architecture provides a fast pixel hit indirect addressing scheme with multiple Time Stamp Registers (TSR). Each TSR is connected to the pixel cells in the column on a separate link. The pixel readout in the chip is chronologically organized by TS. Within the column the readout is organized by taking into account the pixel's physical location. A pixel grouping technique with a two level of hierarchy token passing provides a simple and very fast way of locating hit pixels during the readout cycle. The number of readout controllers, the number of TS registers, the clock frequency of the communication channels, and the depth of the on chip buffers are critical in the design of the architecture. 

As said, the readout speed is critical to the current design. The speed of the links provides a mean readout hit rate. However, the detector has dynamics and the readout system must be able to deal with it minimizing the hit overflow. Here overflow is defined as the number of hits that exceeded the capacity of the system. The present work models the proposed architecture as a Marcovian stochastic process. The design variables are optimized based on known hit distribution functions in the BTeV detector. In the case under study, the pixel architecture can be modeled as a compound discrete-parameter Marcov chain. The number of TS registers and the depth of the FIFOs size the number of states in the Marcov process. The pixel hit rate, the number of pixel readout controllers and the communication channel bandwidths constrain the probability distribution functions of the stochastic process. The results of the present paper show very low overflow rates even for large chips and high accelerator's luminosity.

After the theoretical approach, the pixel readout architecture was validated with simulations. The input data corresponds to Monte Carlo simulations of the detector. The data was generated for two minimum bias particles per beam crossing at a luminosity of 2*10exp32 n/cm². The input data simulates 4000 beam crossings.

The simulations of the pixel readout architecture look at the same variables used in the modeling. That is: clock frequency of the communication links, pixel hit rate, number of time stamp register and readout controllers, and FIFO depth. The results provide statistics on communication link and column occupancy, token passing delay, dynamics of hits in the pixel array, TS registers, and FIFOs , column overflow, and duplicate pixels.

The results show a great deal of consistency with the theoretical approach. They also show that the architecture is very capable of reading and processing the data generated by the simulations. 



References:

[1] BTeV: An Expression of Interest for a Heavy Quark Program at C0, BTeV collaboration, Fermilab, May 18, 1997.

[2] FPIX1 Pixel Readout Chip, A.Baumbaugh, D.Christian, G.Cancelo, J.Hoff, A.Mekkaoui, R.Yarema, S.Zimmerman, Fermilab Internal Document, Feb. 11, 1988.


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Abstract
This paper analyzes in detail some theoretical aspects in the modeling of a readout architecture for pixel detectors. The readout architecture is designed for a column-based pixel detector amplifier and discriminator chip containing more than 3000 pixels of 50 x 400 m. Several readout strategies are analyzed searching for an optimal design, which minimizes data loss and maximizes throughput.
In particular, the probability of loosing pixel hits by overflowing the readout system is minimized modeling it as a stochastic Marcov process. The pixel front-end and readout are simulated and tested with Monte Carlo data. Simulation allows optimizing the communication channel bandwidths and local buffering. The simulated probability of system overflow is confronted with the one obtained by modeling. 

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