Zoltan Meggyesi, Erik van der Bij, Robert McLaren
CERN
!!
Programmable technologies are used in many applications in LHC electronics because of attractive attributes: good density, moderate speed, low cost and quick turn-around time. Some programmable logic devices, like most antifuse based FPGAs, are tolerant to the low or moderate radiation dose rates which are present at most ATLAS Front-End Link locations. However, these chips may have transient errors termed Single Event Upsets (SEU) caused by energetic particles. Logic design methods like redundant design or error detection reduce the probability of malfunctions caused by transient energetic particles will be investigated.
We have developed a datalink card that can be used as a Test Data Generator for on-line radiation testing or as a simplex S-LINK Link Source Card using the HP G-Link as physical layer. The circuit's actual function depends on the configuration of the Actel FPGA. All of the used electronic components are COTS devices on which radiation tolerance data is available.
In Test Data Generator mode the FPGA generates test data for the G-Link and additionally generates 4 bits test signals in order to monitor the internal logic behaviour. The FPGA logic contains data generators composed of loadable shift registers implemented with different design techniques such as single registers or triple modular redundant flip-flops. Internal comparators detect errors occurred in the data generation. The comparison result is transmitted via radiation hard RS-422 drivers and twisted pair cable connections to a Labview based data analyser in the control room. This test method ensures a moderate signalling rate on the twisted pairs going to the control room and full speed (40Mhz, the LHC bunch-crossing frequency) operation of the internal logic circuits. High speed operation of the internal logic is essential during the test because the SEU probability in sequential logic is proportional to the clock frequency. The error ratio between the different design methods will be established.
In Link Source Card mode parallel data from the card's S-LINK connector is processed in the FPGA: data is re-timed and parity bits are added. The data is then serialised by the G-Link transmitter chip at a maximum data rate of 1.6 Gbit/s. Serial data is sent to the media interface which is a coaxial connector for electrical media or a 9-pin standard laser transceiver for optical media. The simplex G-LINK Link Destination Card with built-in data checker and optical power meter can be used as receiver.
We aim to complement work done by others for selecting radiation tolerant serialisers, media interfaces and fibre. Results of irradiation tests on the media components will be presented.
This card will be first irradiated in the TTC2 area of the SPS accelerator in a low dose rate environment. We are also planning to irradiate the components of this card separately in a well-focused proton beam.

!!
We have developed a prototype datalink board in order to test Single
Event Upset mitigation techniques in a programmable logic device and
to investigate the adequacy of the selected devices for the ATLAS
Front-End links. We used only COTS devices on which radiation 
tolerance data is available. Different digital design methods
for transient error elimination in an FPGA will be compared and
radiation tolerance of the serialiser and media interface will be 
tested. Our card can also be used as a simplex S-LINK Link Source
 Card using G-LINK as physical layer with optical or electrical media.
!!