E. Cantatore, CERN Geneva F. Corsi, DEE Politecnico di Bari C. Marzocca, DEE Politecnico di Bari G. Matarrese, DEE Politecnico di Bari !! In the Alice Inner Tracking System (ITS), a huge number of pixel channels is required to ensure the needed resolution. As a consequence, a high degree of uniformity between pixel read-out cells is mandatory to reduce channel-to-channel threshold dispersion and optimise time-walk performance at the system level. The unavoidable device parameter fluctuations cause variability in the characteristics of the front-end circuits employed in the pixel read-out cells and thus degradation of the overall detector performance. The major difficulty that must be addressed to study this problem is to account for the correlation between model parameters, both for transistors of the same kind (i.e. NMOS or PMOS) and of different types. To perform realistic statistical simulations the use of techniques such as the Principal Components Analysis is needed to preserve parameter correlation. In our work the main device parameters have been described by means of principal components and the "corner" points in the parameter space have been found by using an innovative procedure which requires far less computation time than a full Monte Carlo analysis. Each parameter is fixed at its upper or lower bound (+- 3 sigma), and a set of principal components is calculated which provides the chosen value of the parameter. The extraction of this vector is performed by means of a least square method based on the pseudo-inversion of a matrix: in this way the extracted vector of principal components has minimum norm. The values of the remaining parameters are then calculated on the basis of this vector of principal components and, by repeating the process for each parameter fixed at its extreme values, a set of 2n corner points in the parameter space is found. In this way correlation properties between parameters are preserved while calculating the corner points. A selection of basic building blocks has been considered to test the effectiveness of this technique and to compare the robustness of different circuit solutions against parameter fluctuations. A digital inverter, an inverter with active load, a straight cascode, a folded cascode and a simple OTA with active load have been included among these benchmarks. Some relevant performances such as voltage gain and output offset have been studied on these circuits and used to compare them (see table 1). Performance spread Cascode Folded Cascode OTA Output offset [%] 54.01 47.71 32.31 Voltage gain [%] 6.95 2.29 0.29 f-3db [%] 34.20 11.15 5.63 Table 1. Performance comparison of three basic amplifier stages. Starting from the correlation matrix for the main parameters of the model chosen for the MOSFETS (Philips Mos Model 9), the corner points have been extracted with technique described above and the Worst Case Analysis has been performed for all the circuits. The results of this analysis are in good agreement with the worst case performances predicted by a complete Monte Carlo simulation, carried out still taking into account the correlation between parameters by means of the Principal Component Analysis. In table 2 the results obtained following different approaches are compared for a digital inverter. Performance spread PCA Monte Carlo PCA Worst Case Worst Case Input offset [%] 4.96 3.60 7.66 Inversion voltage [%] 4.48 3.13 7.61 Gain [%] 5.38 4.03 7.29 High noise margin [%] 9.81 7.93 15.45 Low noise margin [%] 12.23 10.91 20.91 Table 2. CMOS digital inverter: comparison between different analysis methods. Furthermore, a test pattern containing all the studied basic building blocks has been designed and implemented in a 0.35um process. Measurements performed on a statistically significant number of such circuits allow us to confirm the simulation results, validating the proposed Worst Case Analysis and assessing the relative robustness of the building blocks under study. References 1. E. Cantatore, M. Campbell, et al., "Statistical analysis and optimization of delay line chains for pixel readout electronics", Nucl. Instr. and Meth. in Phys. Res. A 395 (1997) pp. 318-323. 2. M. Pelgrom, A. Duinmajer and A. Welbers, "Matching Properties of MOStransistors for precision analog design", IEEE Trans. Solid State Circuits 24 (1989) pp. 1433-1440. 3. M. Bolt, E. Cantatore, M. Socha, C. Aussems and J. Solo, "Matching Propertiesof MOS Transistors and Delay Line Chains with Self-Aligned Source/Drain Contacts", Proceedings of the ICMT'96, Trento - Italy (March 1996). 4. C. Michael, M. Ismail, "Statistical modeling for computer-aided design of MOS VLSI circuits", Kluwer Academic Publishers, 1993. 5. D. Bini, M. Capovani, O. Menchi, "Metodi numerici per l'algebra lineare", Zanichelli Bologna, 1988, pp. 456-462. 6. E.V. Saavedra Diaz, K.G. McCarthy, D.B.M. Klaassen and A. Mathewson, "Efficient parameter extraction and statistical analysis for a 0.25 micron low-power CMOS process", Proceedings of the 27th European Solid-State Device Research Conference (ESSDERC'97), pp. 656-659,1997. 7. M. Bolt, M. Rocchi, and J. Engel, "Realistic Statistical Worst-Case Simulations of VLSI Circuits", IEEE Trans. on Semiconductor Manufactoring, vol. 4, n. 3, August 1991, pp. 193-198. 8. S. R. Nassif, A. J. Strojwas, and S. W. Director, "A Methodology for Worst-Case Analysis of Integrated Circuits", IEEE Trans. on Computer-Aided Design, vol. cad-5, n. 1, January 1986, pp. 104-112. 9. C. Michael, M. Ismail, "Statistical modeling of device mismatch for analog MOS integrated circuits", IEEE Journal of Solid State Circuits, vol. SC-27, February 1992, pp. 154-166. !! The large number of channels (15.7 millions), needed for the silicon pixel detector under development for the ALICE ITS, requires a careful study of the statistical fluctuations of the front-end electronics performance. By means of classical techniques, such as the Principal Component Analysis, and of new ones used to obtain a realistic "Worst Case Analysis", various configurations of basic CMOS amplifiers stages have been compared to evaluate the relative robustness of their performance against manufacturing fluctuations. To validate the simulated results on a significant statistical sample, a test pattern containing these basic building blocks has been designed and implemented in a 0.35um CMOS process. In this work we present both the theoretical results and the experimental ones, obtained characterising the test chip. !!