V.V.Souchkov, University of California Riverside
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Precise timing is important in modern collider experiments both for tracker and TOF detector subsystems. Several discrimination techniques (starting with classical constant fraction discriminator CFD) have been developed in the past to make timing insensitive to the detected signal amplitude. These techniques are comparatively discussed in this study with respect to their noise behavior.  In many cases front-end noise appears to be not a negligible contribution to timing (time jitter). When this is the case the right choice of the type of discrimination technique and determination of optimal parameters for the processor employing particular technique are of major importance. When realizing one or another kind of discriminator on chip one has to understand the limits imposed by the circuit approximations of an ideal processor. 
The use of different discrimination techniques and low-noise front-end, processing signals in nanosecond range may require tentative choice of processor parameters to achieve better time resolution. Computer methods employed for the analysis different strategies in discriminator realization are discussed. 
 At the beginning semi-analytical approach in time jitter derivation in case of classical CFD is discussed. The approach takes advantage of interfaces to standard electronic simulators and gives the possibility to bypass a bulky procedure of carrying out parametric analyses of numerous runs with circuits representing
delay line, fraction and ideal difference introduced into simulations. The signal processor part  representing discriminator is considered to be noiseless, however derivation of time jitter is based on noise spectral density of the front-end referenced to the discriminator input. Time jitter dependence on  fraction and delay are determined  for the whole range of these parameter variations after two simulation runs. 
 The developed method of jitter calculation is extended to double fraction discriminator and time stamp derivation with time variant filtering. For the above cases the goal functions giving similar dependence are built. Finally several methods of on chip discriminators realizations of the above types are discussed comparatively to classical fraction discriminators.


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This study is motivated by intention to characterize electronic noise contribution of an arbitrary front-end to timing (time jitter), when a nanosecond signal processor involving one or another type of discrimination techniques is in use. Discrimination techniques for which time stamp determination is insensitive to the detected signal amplitude are discussed in connection to their possible on-chip realizations. Semi-analytical approach developed in this work takes advantages of standard interfaces to modern electronic simulators. The proposed modeling of discrimination techniques provide rapid evaluation of front-end noise contribution to timing for any of the discussed techniques. 

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