M.Raymond, G.Hall, Imperial College, London, UK.
M.French, L.Jones, A.Neviani, Q.Morrissey, Rutherford Appleton Laboratory, UK.
P.Moreira, G.Cervelli, CERN, Geneva, Switzerland.
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The CMS inner tracker contains approximately 10 million channels implemented in silicon and gas microstrip technologies, read out by APV chips. For several years now these chips have been developed [1,2] to meet the demands of low-noise, low power and radiation hardness required for operation at the LHC. More recently it has been demonstrated that commercial deep submicron CMOS technologies currently available may exhibit radiation tolerance to levels in excess of those required [3], together with the possibility of operating with low noise and power consumption, as well as increased circuit density. Because of the potential for improvements we have embarked on a rapid development programme to produce a prototype APV chip in a deep submicron technology.

The APV25 chip has been designed in a 0.25 micron CMOS process and is very similar in concept to previous APV chips. It has 128 readout channels, each consisting of a 50 nanosecond CR-RC type shaping amplifier, a 192 element deep pipeline and a pulse shape processing stage which can implement a deconvolution operation to achieve the single bunch crossing resolution necessary at high luminosities. Analogue output samples are then multiplexed onto a single differential output for subsequent optical transmission to the DAQ system. The output data frame consists of these analogue samples preceded by a digital header which includes a digital address of the pipeline column from which the data originates. The chip can operate in one of three modes. In peak mode, following an external trigger, one sample for each channel (timed to be at the peak of the amplifier output pulse shape) is read from the pipeline and subsequently output through the multiplexer. In deconvolution mode three samples/channel are read from the pipeline and combined in a weighted sum before output. In multi-mode a sequence of external triggers allows a number of consecutive pipeline samples to be transmitted in consecutive output data frames.

The pipeline is used to store the amplifier outputs, sampled at the 40 MHz LHC frequency, while external trigger decisions are taken. The pipeline depth allows a programmable latency of up to 160 bunch crossings (4 microseconds) the remaining locations being used for buffering of data from up to 10 events (in deconvolution mode). For technological reasons the pipeline storage elements have been implemented using gate capacitance which allows a very dense layout for this memory array.

The APV25 deep submicron CMOS chip contains all the necessary system features, including on-chip bias and calibration pulse generation, and a slow control interface for programming these features and the operating mode of the chip. The active chip area is approximately 6.5 mm x 7 mm. In this paper we will present details of the design and the measured performance of the chip.



References:

[1] The APV6 Readout Chip for CMS Microstrip Detectors, M.Raymond et al, Proceedings of 3rd workshop on electronics for LHC experiments, CERN/LHCC/97-60, 158-162.
[2] Performance of a CMOS Mixed Analogue-Digital Circuit (APVD) for the Silicon Tracker of CMS, F.Anstotz et al, Proceedings of 4th workshop on electronics for LHC experiments, CERN/LHCC/98-36, 180-184.
[3] Total Dose and Single Event Effects (SEE) in a 0.25 micron CMOS Technology, F.Faccio et al, Proceedings of 4th workshop on electronics for LHC experiments, CERN/LHCC/98-36, 105-113.

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The APV25 is a 128 channel analogue pipeline chip for readout of silicon microstrip detectors in the CMS tracker at the LHC. Each channel comprises a low noise amplifier, a 192 cell analogue pipeline and a deconvolution readout circuit. Output data are transmitted on a single differential output via an analogue multiplexer. The chip is fabricated in a 0.25 micron CMOS process to take advantage of the radiation tolerance, lower noise and power, and high circuit density which can be achieved. The chip design and test results will be presented.
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