R. Baur, R. Horisberger, R. Schnyder (PSI Villigen)
W. Erdmann, M. Hilgers, B. Meier (ETH Zurich)
!!
The Readout Architecture of the CMS Pixel Detector:

           The CMS Pixel Detector will provide 3-dimensional tracking points for a 
precise impact parameter measurement in r-phi and z-direction in order to improve the
recognition of secondary vertices. The end disk and barrel layers are composed of approx. 
40 million individual pixel cells with a size of 150um*150um. An analogue readout of hit 
pixels allows a high spatial resolution of ~15 um in r-phi and z-direction.

           The final readout chip consists of 53 * 52 pixel cells. Each pixel cell is 
comprised of a low noise preamplifier, a shaper with 25 ns peaking time and a comparator 
circuit with individually trimmable thresholds. The comparator output is used to store the 
pulse height information and to signal, via a wired-OR line, a pixel hit to the peripheral 
control circuit.  A readout concept suitable for such a large system is based on a column 
drain architecture. Pixel cells of individual chips are grouped into double columns of 
2 * 53 pixels. The readout is initiated if one or more pixels are hit. A fast token-skip 
algorithm searches along the double column for pixel hits and and copies their analogue 
data to peripheral data buffers. Data resides there for bunch crossing identification 
and level-1 trigger verification.

           Many of the critical functional blocks have been designed and submitted in the 
radiation hard TEMIC/DMILL 0.8um technology as individual test structures and tested 
before and after irradiation: 
(i)  We have implemented the fast token bit search scheme and measured a 1.2 GHz skipping 
frequency of unhit pixels after irradiation.
(ii) The analogue data transfer from the pixel cell to the data buffer has been studied 
and verified to cope with our requirements.
(iii) The data buffer management allows to allocate varying buffer sizes for different 
events. By this we can keep the number of data buffer cells lower as compared to a fixed 
assignment. In a prototype circuit all functions like simultaneous read/write-operation, 
data formatting and readout of level-1 verified hits with coded pixel address headers 
have been implemented and we verified the full functionality of the circuit.
   
            One of the crucial points in this architecture is to ensure that the
hit search and data transfer in the pixel cells do not cross-talk into neighboring, 
originally unhit, pixels. In order to study this in a realistic environment (with e.g. 
bump-bonded detectors), a test chip (DM_PSI36) has been developed. It consists of a 22*30 
pixel array, with the full column drain architecture implemented. Compared to the final 
architecture the reduced column periphery of this chip uses the same readout scheme for 
the transfer of the analogue data to the periphery. There is only one storage cell per 
double column is available. The fast hit search continues once the data buffer cell is 
read out.

           In the last part of this talk we will present first measurements of single 
event upset rates performed in the low energy pion environment at the PSI p-E1 beam-line. 
Test flip-flops in DMILL technology with different layouts and supply voltages have been 
studied. In addition we will present a relative comparison of single event upset rates of 
similar designs produced in TEMIC/DMILL and Honeywell/RICMOS 0.8u technologies.


!!
The CMS Pixel Detector is composed of approx. 40 million pixel cells 
with analogue readout. In a column drain architecture (CDA) a fast 
token-skip algorithm searches along a double column for pixel hits 
and copies analogue data to peripheral data buffers. The data buffer
management allows to allocate varying buffer sizes for different events.
Test structures have been implemented and show full functionality. 
In a 22*30 test chip (DM_PSI36) the full CDA has been implemented and 
cross-talk problems have been studied with bump-bonded detectors.
We will present first measurements of single event upset rates in DMILL 
technology performed at the PSI pion beam-line. In addition a comparison
of SEU rates of similar circuits produced in 0.8u TEMIC/DMILL and 
HONEYWELL/RICMOS will be shown.

!!