F. Faccio(1), K. Kloukinas(1), G. Magazzu(2), A. Marchioro(1)
(1) CERN, Geneva, Switzerland
(2) INFN, Pisa, Italy

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The environment around particle detectors in future LHC experiments requires not only technology and design techniques able to withstand large total doses of ionizing particles and fluxes of neutrons, but also special design precautions to avoid losing information stored in digital storage circuits such as registers and random access memories.
A typical LHC detector such as the CMS central tracker contains of the order of (100,000 chips * 100 registers * 10 bit/register = ) ~ 10^8 bits of state information, and delivers an equivalent of (100,000 chips * 100,000 events/sec * 128 channels * 1 sample/event = ) ~ 1*10^12  samples/sec of information. When hitting critical nodes in embedded ASICs heavily ionizing particles can flip the information in configuration and state registers or modify the (digital or analog) data being read. Depending on the node being hit, such an event can have potentially serious effects.
Several techniques have traditionally been proposed to overcome the problem, ranging from using special technologies using isolating substrates such as SOI or silicon-on-sapphire to adopting robust design layout rules. Our work used this last approach on a commercial deep-submicron technology.
A large array of 128*144 bits of SRAM has been designed with radiation tolerant layout rules. Despite the very conservative approach required, a basic dual-ported memory cell of 10x5.6 um^2 has been obtained allowing to pack the entire array in less than one square millimeter, including decoders and selection logic. This is about four times larger than what could be obtained by using the same technology design rules for a non-rad-hard single port memory cell. The design has not been optimized for speed, but for SEU resistance, at the expense of some extra power. Minimum size gates (and therefore capacitance) have never been used in the circuit. The design methodology includes both static and, for area saving, dynamic circuitry. Special precautions have been taken to make dynamic gates robust to SEU. 
The memory floor-plan is arranged to avoid double bit losses in the same memory word. This requires a somewhat more elaborate write logic, but results in a structure where the occurrence of a double bit error can be recognized via simple parity logic. With the addition of a straightforward external logic block using the rad-hard standard cell library, the memory can be configured as a FIFO for typical applications in read-out ASICs.
To the user, the Dual Ported Memory presents input registers for addresses and input data and starts a cycle on the rising edge of the clock signal. The output is not latched and is directly available to the user.
The results in total dose irradiation and SEU cross section will be given.

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A dedicated high speed 2 KB memory featuring synchronous mode, parity and dual port access has been designed and fabricated in a quarter micron 3 metals CMOS technology. This memory is a building block for a high speed optical link interface ASIC being designed at CERN. However it can be used also as a generic building block for read-out buffers or FIFOs. The RAM has a typical access time of less than 10 ns and uses a mixture of static and dynamic logic.
The RAM has been designed as a test vehicle to measure Single Event Upset effects on a real circuit. Measurements on D-type flip-flops realized in the same technology had previously shown an LET threshold up to 89 MeV gr-cm-2. The LET measurements using different ion species on the new circuit will be reported. The techniques used to improve the SEU resistance will be described and indications on the bit error rate to be expected for a typical LHC environment will be given.

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