University of Catania and INFN Sez. Catania
Corso Italia,57 I-95129 CATANIA - Italy

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According to our simulations a preamplifier-shaper has been designed. It has 8 channels. Each
channel consist of a charge preamplifier and a CR-RC shaper to limit noise. Thermal and shot
noise has been simulated as 300 e-. Since the  leakage current foreseen is not more them 10 nA. To have the foreseen 7 Mip range the preamplifier has a sensitivity of 155 mV/MIP. The shaper has a gain of 1 V/V and a driving capability of 7 pF as required by the 256-cell  Analog  Memory.

A 16 channels 256 cells analog memory has been realised as a switched capacitor array. It works as an analog delay line. The read frequency is 1 Mhz driving 15 pF output load and the write frequency is 40 Mhz. The circuit has to be tested. The previous prototype (64 cells 3 channels) working at the same write and read frequenciy showed during tests the expected performances. Dynamic range 0.5 - 4 V, Linear Range 1.5 - 3.5 V ( ~ 6 mV) Dc gain 0.9988.
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In this system the signals coming from each anode of  the detector are sent to one input of an Preamplifer-Shaper (PAS)  whose  outputs are connected  to the inputs of  an Analog Memory (AM). The AM must continuously sample the analog signals at 40 MHz (the bunch-cross rate) and store all the data. When some suitable condition is detected, a trigger signal stops the write phase. Than a read phase begins the transfer, at low rate (1 MHz) the data to an  other chip that perform  digitalization.
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