R. E. Blair, J. W. Dawson, W. N. Haberichter, J. L. Schlereth, Argonne National Laboratory
M. Abolins, Y. Ermoline, Michigan State University
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In an effort to reduce data transfer and rate requirements, the Second Level Trigger (SLT) of the Atlas Detector was originally envisioned to use Region of Interest (ROI) information forwarded to Level 2 on a Level 1 Accept.  The Level 1 Trigger is organized as a number of partitions, perhaps as many as 12.  On a Level 1 Accept each partition prepares and transfers to Level 2 an ROI fragment via S-link which pinpoints interesting elements of the event within a specific subdetector of Atlas.  The function of the ROI Builder is to receive these ROI fragments, which may be considerably skewed in time and may be interspersed with fragments from other events.  It must organize and format a complete record for each event accepted by Level 1 from these fragments, select a processor in the Level 2 Supervisor to manage the event through the SLT, and transfer via S-link the assembled ROI record to the target processor. The ROI Builder must fulfill these requirements at the Level 1 Trigger rate of 100 KHz while accommodating S-link flow control.  A design for this prototype ROI Builder was developed emphasizing parallelism, and implemented in FPGA's.  This prototype was built and has been operated in test beds at Argonne, Saclay, and CERN.  This paper describes the design and operational performance of this Hardware ROI Builder.
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In an effort to reduce data transfer and rate requirements, the Higher Level Trigger of the Atlas Detector uses Region of Interest (ROI) information forwarded from Level 1 Partitions on a Level 1 Accept.  The ROI Builder receives these ROI fragments, which may be considerably skewed in time and may be interspersed with fragments from other events, organizes and formats  from these fragments a record for each event accepted by Level1,  selects a processor to manage the event, and transfers via S-link the assembled ROI record to the target processor. The ROI Builder must fulfill these requirements at the Level 1 Trigger rate of 100 KHz while accommodating S-link flow control.  A design for the ROI Builder was developed emphasizing parallelism, implemented in FPGA's, and has been run  in testbeds at Saclay and CERN.
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