P. Placidi - CERN/EP, University and INFN of Perugia
K.Kloukinas -- CERN/EP
A. Marchioro - CERN/EP
P. Moreira - CERN/EP

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The CMS central tracker electronics operates synchronously to the 40 MHz LHC master clock which is encoded with the first level trigger in a signal distributed from a single central source. This encoded signaling scheme minimizes the bandwidth and the power requirements on the transmission system but needs a dedicated circuit to recover the clock and trigger signals. The recovered clock is used on the front-end APV ASIC for data sampling. Jitter of less than 0.5 ns is required not to compromise precision of the measurement. As the circuit has to be used in an environment close to the very sensitive front-end analogue electronics, it is necessary to reduce the generated switching noise. This circuit has to operate in an environment where, due to the large number of readout channels, the power consumption has to be minimized. Moreover, the central tracker is also a region that exhibits the most severe radiation conditions in CMS.
To meet the tracker radiation constraints, the IC has been implemented using radiation tolerant layout techniques.
To recover the clock and the trigger signals a dedicated ASIC has been designed in a 0.25 mm CMOS technology. The ASIC provides also the possibility to select the clock and the trigger phase in steps of 1 ns. Additionally, the trigger signal phase can be delayed in multiples of the clock period up to a maximum of 16 cycles.
The core of this ASIC is a 40 MHz Phase-Locked Loop (PLL) working at 2.5 V and using a self-calibration techniques to minimize dependence on process variations and to allow auto-calibration of the devices due to new operating conditions, for instance after radiation induced damage.
The PLL consists of the following major blocks: 

-a double mode digital phase detector, working as a Phase Frequency Detector (PFD) during the lock acquisition and as a Phase Detector (PD) once the lock is acquired;
-a charge-pump circuit, converting the signals from the PFD/PD into a control current;
-a loop filter, integrating the charge-pump current and controlling the loop dynamics;
-a constant amplitude, differential Voltage Controlled Oscillator (VCO), to minimize noise and power supply dependence of the oscillator frequency.
-a digital auto-calibration circuit used to compensate for process variations by comparing the incoming clock frequency and the free running VCO at startup.

A previous prototype version of this IC was fabricated using a non rad-hard 0.8 mm BiCMOS technology resulted in an area of 2.6x2.1 mm2, where roughly half of the area was used by digital standard cells. In this new version the area occupied by the digital standard cells has been reduced by a factor of 8 while the full custom part is reduced by a factor of 2. Moreover, due to the reduction of power supply voltage the power consumption has been reduced by about 40 %.
The ASIC design requirements and the main test results will be reported; special emphasis will be put on the evaluation of the effects on the circuit functionality and performance of the total dose and the single event upset phenomena.

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The clock and first level trigger signals used in the CMS central tracker are transmitted as a single 40 MHz square wave that presents a missing pulse when a trigger occurs.  This paper describes the design of a dedicated, low power and low jitter Phase Locked Loop ASIC in a 0.25 mm CMOS technology. The ASIC recovers the clock and trigger signals meeting the CMS tracker power budget and radiation hardness constraints.  In the design of this ASIC a self calibration techniques is adopted to accommodate for process variations and devices parameters changes due to radiation damage.  Design requirements and test results will be reported; the evaluation of radiation effects on the ASIC performance due to total dose and single event upset phenomena will be presented.
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