A. Rivetti, G. Anelli, F. Anghinolfi, M. Campbell, M. Delmastro, E. Heijine, F. Faccio, S.
Florian, P. Jarron, K. Kloukinas, A. Marchioro
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Present state-of-the-art CMOS technologies integrate MOS transistors with a minimum gate
length of 0.18?m - 0.25 ?m and operate with a maximum power supply of 2.5 Volts. At the same
time technologies operating at 5V power supply are being gradually phased out.

In the LHC experiments, a very high level of integration and low power consumption are
required for the front-end electronics. This makes deep-sub-micron CMOS technologies a very
attractive option for ASIC design. Moreover, we have developed layout techniques which
strongly enhance the radiation tolarance of these processes.

The design of analog electronics in deep sub-micron CMOS entails however a number of issues.
Deep sub-micron technologies are mainly used for the fabrication of digital circuits in large
volume and sometimes the qualification of the analog parameters of the technologies by the
manufactures is not completely adequate. The reduced power supply voltage presents new
challenges for analog designers: the available dynamic range is reduced and low voltage
design techniques (rail-to-rail circuits, current mode processing) may be required. These may
entail a significant increase in circuit complexity. 

This work began with the study of device characteristics which are of primary concern for
analog design. In particular noise performance and matching properties of MOS transistors
have been investigated in detail, as well as the characteristics of integrated capacitors
(both poly-to-diffusion and metal-to-metal capacitors). The noise excess factor (ideally = 1)
is around 1.5, which is fully compatible with low noise analog design. 

To study the advantages and limitations of deep sub-micron technologies for LHC applications
some test circuits have been designed. As demonstrator circuits, we have chosen a
preamplifier, an analog memory and an analog to digital converter. 

The preamplifier has a transimpedance architecture and has been optimized for detector
capacitance of 5pF. Measurements show that the preamplifier achieves a gain of 40mV/MIP with
a peak to peak output noise of 4mV, a peaking time of 7ns and power consumption of 1mW.

The main goal of the analog memory circuit is to investigate the use for the memory cells of
polysilicon-to-diffusion capacitor, which in deep sub-micron become very dense and allow
therefore a very compact design. The drawback of these capacitors is the voltage dependence
of their absolute values: for this reason we choose a classical voltage write/voltage read
architecture which minimizes the influence of the capacitor nonlinearity.

The analog to digital converter uses a successive approximation switched capacitors
architecture. Since in this circuit the capacitor linearity is crucial metal to metal
capacitor are used. The ADC has been designed for a resolution of 10 bits and a conversion
speed of 4 Megasample/sec, with a power consumption estimated to 4mV.
!!
The feasibility of analog integrated circuits for LHC experiments in deep sub-micron CMOS
technologies has been addressed through the design and test of circuits widely used in
particle physics applications such as preamplifiers, switched capacitors analog memories and
analog to digital converters. In addition a systematic study of fundamental analog
characteristics of commercial deep-sub-micron CMOS processes is presented. Noise performance
as well as matching properties of devices have been investigated. Design issues related to
the intrinsic characteristics of sub-micron processes (reduced power supply, availability of
many level of interconnections) are identified and discussed 
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