P. Moreira, J. Christiansen, A. Marchioro, K. Kloukinas, G. Cervelli and M. Campbell
CERN-EP/MIC		
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Several LHC detectors require high-speed digital optical links for transmission of data between the different detector subsystems and the control room. Typically, high-speed data transmission is required for both the trigger system data path and the data readout systems. Commercial of the shelf components can be found that meet the bandwidth requirements of most of these systems. However, they fail to meet one or both of the following requirements frequently encountered in the LHC-HEP environment: resistance to high radiation doses, up to 10 Mrad for components located in the central tracker detectors and, synchronous transmission of data (constant latency), for trigger systems. To address this problems, a high-speed (1.2Gbit/s) transmitter prototype IC has been developed. This prototype was specially conceived for data transmission in trigger systems allowing synchronous transmission of data at rates compatible with the LHC bunch-crossing frequency (a feature not necessarily available in all the existing data communications chip-sets). However, the operating data rate and the data framing have been chosen close enough to the industrial Gigabit Ethernet standard so that the transmitter can also be operated at a standard data-communications frequency (1.25Gbit/s) permitting testing using commercial equipment. Additionally, this allows the IC to be used in conjunction with standard chip-sets for applications were synchronous transmission is not essential, e. g. event building, thus enlarging the users choice and allowing for flexible system development.
Data transmission will be encapsulated in an 8B/10B line-coding scheme. This will results in an effective data rate of 960Mbit/s when the transmitter is operated in the synchronous mode at 1.2GHz (30 times the LHC clock frequency). For asynchronous operation, a 1Gbit/s effective data bandwidth can be achieved when the standard 1.25GHz clock frequency is used.
The developed prototype contains the most critical functions of the transmitter. These include a serializer that transforms 10bit parallel words into a 1.2Gbit/s (or 1.25Gbit/s) serial stream. A clock multiplying PLL that generates the internal 1.2GHz (or 1.25GHz) clock from the 40.08MHz LHC clock. The IC contains also a high-speed 50Ohm (PECL like) driver that allows the chip to interface with most common optical transceivers. The IC features a low operation voltage (2.5V) contributing to low power consumption. 
The IC has been implemented in a standard 0.25um CMOS process using well-established radiation tolerant layout practices. ICs designed in the past with such a process and layout techniques have proven to be radiation resistant to high levels of total dose irradiation. Measurement results will be presented on both the system performance and on the tolerance to the total dose radiation effects. The susceptibility to single event upsets will also be the object of study.

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Several LHC detectors require high-speed digital optical links for data transmission in both data readout and trigger systems. Commercial of the shelf components can be found that meet the bandwidth requirements of most of the LHC detectors subsystems. However, they fail to meet some of the requirements frequently encountered in the LHC-HEP environment: resistance to high radiation doses and operation tolerant to single event upsets. To address these problems, a high-speed transmitter IC (1.2Gbit/s), containing a serializer and a clock multiplying PLL, was developed. The prototype allows synchronous and asynchronous (Gigabit Ethernet compatible) transmission of data and it was designed using well-established radiation tolerant layout practices in a standard 0.25um CMOS technology to achieve resistance to high radiation doses.
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