G. Braun, H. Fischer* J. Franz, A. Griinemaier, F.H. Heinsius, L. Hennig,
K. K6nigsmann, M. Schierloh, T. Schmidt, H. Schmitt, H.J. Urban
Fakultit ffir Physik, UniversitAt Reiburg, 79104 Reiburg, Germany
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We describe a new dead-time free eight channel Time-to-Digital Converter (TDC) initially developed for the COMPASS experiment at CERN. This new ASIC, the F I-TDC, is based on a 0.6pm sea-of-gates CMOS process. Excellent time resolution, high rate capability, low power consumption and wide flexibility due to in-system programmable setup registers let the chip appear as an ideal candidate for many applications in LHC experiments such as tracker or time-of-flight detectors. Feasibility studies for the LHCb outer tracker have started recently.

The heart of the TDC is an asymmetric ring oscillator controlled by a phase locked loop. A chain of 19 delay elements is used to tap time digitization in steps of 120 ps. The width of the digitization steps can be adjusted by ±20%. In combination with a coarse counter the dynamic range of the TDC is extended to 16 bits. To improve digitization to 60 ps two channels of the TDC can be interleaved internally. In a different mode, provided for multi-wire proportional chamber readout, 32 input lines are latched in groups of four to the eight TDC channels. In this case the resolution is 5 ns, and the last four bits of the time stamps are used to flag hits on the four connected lines.

The architecture incorporates two distinct digitization modes: start/stop and trigger correlated, respectively. In the start/stop mode an experiment wide synchronization signal defines time zero and all subsequent hits (leading and/or trailing edges of signals) are recorded relative to the last synchronization signal. All recorded time stamps are passed to the TDC output. In the trigger correlated readout mode a selective signal, based on physics conditions of an experiment, is distributed and its time is measured by the TDC, too. Only time stamps which are correlated with the trigger signals are passed to the output interface. The trigger window boundaries can be programmed freely at start-up time.

A four word deep trigger FIFO accommodates for high instantaneous trigger rates. All received triggers are registered and counted even if high trigger rates for extended periods cause trigger-FIFO full conditions. A special lost-trigger flag in the data header indicates discarded triggers. From the time stamps of the triggers, contained in the data header, the period during which triggers have been missed can be calculated and the chips maintain event synchronization throughout the experiment.

In view of easy integration into distributed detector mounted readout systems the chip is designed with two output interfaces 8 bit and 24 bit wide. The eight bit interface matches the specifications of the 400 Mbit/s HOTLink chip and supports easy serialization of the data. Independent working readout buffers for each TDC channel and a 16 word output FIFO ensure readout with basically no wait states even at highest data throughput.

All features are software programmable during chip initialization by a fast 10 MBaud serial link.

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We describe a new Time-to-Digital Converter (TDC) chip realized in 0.6prn sea-of-gates CMOS technology. A chain of 19 delay elements in an asymmetric ring oscillator, stabilized by a phase locked loop, is used to tap time digitization steps of 120 ps in the standard and 60 ps in the high resolution mode. On-chip arithmetic logic units select hits which are correlated with experiment trigger signals. Several independent working data buffers and trigger matching units guarantee dead time free digitization and readout at highest data rates. Two parallel output interfaces, 24 or 8 bit wide are implemented, where the latter matches the specifications of the 400 Mbit/s version of the HOTLink chip to serialize the data.
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