C. Kiesling, MPI Muenchen
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The extremely high interaction rates expected at the LHC will require highly selective triggers already at the hardware level. Encouraged by the good experience at HERA, where such 
a system is successfully operating since a few years, a neural network architecture of the feed-forward type is proposed for the fast global event decision at the second (or 
higher) trigger level. The strength of the neural approach rests on its ability to exploit the high-dimensional correlations in the input data, thus providing a largely 
improved selectivity with respect to more traditional trigger schemes. The neural computations are executed in commercially available, massively parallel processor arrays, which provide 
the required computing power to solve the pattern recognition task in real time (of order 20 microseconds). Although the processor arrays are designed for fast matrix-vector 
multiplication and summing (accumulation) of the partial products, and are thus optimized for genuine neural algorithms, they can be programmed for more general 
algorithmic computations. Other neuromorphic hardware developments are underway both in industry and in research institutes, so that the processing power of these devices is 
expected to dramatically improve by the time the LHC experiments turn on.   

Special attention is paid to the inputs of the neural networks, for which physically motivated preprocessing steps are foreseen. The preprocessing is completely independent of 
the neural hardware, and a customized development, having in mind a particular experiment (ATLAS), is presented. Since the basic input information comes from the various first level 
trigger processors, it is advantageous for a global event decision scheme to compress the input data to the physically relevant quantities: By combining the information from the various subdetectors, the preprocessing is tailored to provide, at the trigger level, physical objects such as 
`jets'', ``leptons'', or ``photons'' together with their topological information. Via a time-ordered multi-bus system the preprocessors are given access to the entire level 1 (2) 
trigger data from the main components of a typical LHC detector and construct the physical objects as inputs to the neural nets. The basic idea for the data compression is a 
clustering algorithm, finding, e.g., the localized energy depositions and their topological arrangement (“isolation”)  in the electromagnetic and hadronic calorimeters, or hit 
clusters from the tracking chambers. After matching this information in a topological order, the resulting ``objects’’ are stored in a vector (16 bit precision), ordered by 
criteria of choice (e.g. transverse energy), and are then made available as network inputs. The data compression and feature extraction task is executed in dedicated preprocessing hardware, based on modern FPGA technology.

Another interesting neural algorithm under study, to be used in combination with the above physical objects, is a secondary-vertex finder, using the information from the Si-
tracker, available at the second trigger level. In a special preprocessing step, hits associated with tracks are found using associative memory techniques and secondary vertices are reconstructed from the hits using standard feed-forward neural nets. The resolution of the vertex is of order 1 mm, sufficient for the efficient tagging of final states containing heavy flavor decays already at the trigger level.
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A global event decision system, based on the neural network architecture, is presented as a hardware trigger for LHC  experiments. The system is based on commercially available,  massively parallel processor arrays, which provide the  required computing power to solve the pattern recognition task in real time (of order 20 microseconds). Special attention is paid to the input of the neural networks, for which a physically motivated preprocessing step is foreseen,  providing objects such as ``jets'', ``leptons'', or  ``photons'' together with their topological information. This  data compression and feature extraction task is executed in  dedicated preprocessing hardware, based on modern FPGA technology.
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