Müller!!Hans!!Hmuller@mail.cern.ch!!CERN!!CERN  !!CH-1211 Geneva 23!!Division EP!!Switzerland!!LHC-B!!DAQ!!Electronics production and test!!Readout Unit for the LHCb experiment!!990426006

Hans Müller,  CERN / Francois Bal, CERN  / Les McCulloch, CERN /
Jose F. Toledo,  Politechnical University  of Valencia, Spain
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The Readout Unit (RU)is being developed to fulfil the 
functionality of the first stage of the LHCb data acquisition system. 
Its role is to receive event fragments from several front-end links, 
to assemble them into larger ‘sub-events’  and to transmit these to 
the next stage ( the readout network ) for complete event building. 
The RU must be equipped with a LAN connection for remote control  and 
monitoring purposes. 
   
The RU’s quadruple S-link receiver input stage merges incoming 
event fragments into concatenated subevent blocks, using a recursive 
data-format convention. A FiFo-based derandomiser  logic  is used at 
the inputs. For data-link multiplexer applications, the concatenated 
output is available unbuffered on one Slink  transmitter port, using 
a recursive data-format convention.
  
For the  DAQ application as  eventbuilder interface,  the  input  
merger  logic  sorts and  buffers all  incoming event fragments 
according to equal  event-number matches,  together  with a directory 
entry.   The size  of the  subevent buffer  can be increased to allow
for up to 50 ms of flow control  latency via the LAN.  This  buffer  
is logically  operated  by the RU logic like a FiFo, however it is 
physically implemented as a Dual Port Memory ( in order to  allow  
for random access).   Subevents are read from the buffer, reformatted
and  consistency-checked  by an  FPGA-resident eventbuilder  logic,  
which communicates  with  the  eventbuilding protocols of the readout
network across  the PCI  bus.  The queued  subevents  are transferred
from the buffer according to various  transfer mechanisms, which  can
be  implemented according to the readout requirements: automatic  
store&forward,  PCI-adapter based DMA engines or, block moves by the 
I/O processor. The latter handles normally  remote control and 
monitoring via  a 100Mbit/s  LAN connection to the experiment 
control system and  can also  be used  for remote  reprogramming of  
the  FPGA’s  or for enabling or resetting of  I/O  links.  

The flow-through architecture, between up to four Slink  receivers  
and  one  PCI-64 output,  is  conceived to cope with  a minimal 
sustained  bandwidth of 160 Mbyte/s per RU module by using an overall  
64 bit bus architecture to sustain the minimal transfer rate. 
The input and the output stages are implemented as two independent  
FPGA functions which are developed using  VHDL methodology.  We use 3.3 Volt, 
55 kgate  FPGA’s  for the input logic  and  45 kgate FPGAs with  embedded  
64 bit  PCI bus cores for the output stage. The monitoring and control  unit 
is based on a 100 MHz I/O processor  with  integrated,  dual PCI bus architecture.
 
The  prototype is implemented in 9U crate  mechanics of  IEEE 960,  
using only  power from  the  bus connector. There are two PMC 
( IEEE P1386) mezzanine carriers on the rear side for network and 
for auxiliary PCI adapters and four S-link mezzanine carriers on the 
front panel. The auxiliary PCI mezzanine port  allows for extensions 
of  RU applications such as the use of a TTCrx receiver mezzanine. 

We plan the design of an RU module optimised for cost and 
performance, following field experience with first RU prototypes, 
and decisions on the supporting technologies.
!!
The Readout Unit (RU) for  the LHCb data acquisition system is a 
programmable eventbuilder  interface, taking input from up to four  
Gbit/s  link  receivers, and  outputting to single nodes of a  
readout network.  It has been conceived as a versatile and 
programmable  prototype module that uses  the ATLAS  S-link  
technology  as  link  protocol,  9U- IEEE960 power and mechanics, 
and PCI  bus  protocols for the readout network. The  FPGA-based 
receiver stage  merges incoming  event-fragments  into  subevent 
blocks  that  are stored in an intermediate subevent buffer. 
Subevents are forwarded by an FPGA based eventbuilder  interface 
logic   that is directly connected via the PCI bus with the  
protocols of the readout network. An embedded  I/O processor 
provides remote control  over  all  input and output functionalities,
via  a 100Mbit/s  LAN connection to the experiment control 
system.
!!