Yasuo!!Arai!!yasuo.arai@kek.jp!!KEK, National High Energy Accelerator Research Organization!!1-1 Oho!!Tsukuba, Ibaraki 305-0801!! !!JAPAN!!ATLAS!!MU!!R/M field tolerant electronics!!Neutron and Gamma Iradiation Test of the 0.3 um CMOS for the ATLAS Muon TDC!!990427008

Yasuo Arai
KEK, National High Energy Accelerator Research Organization
Institute of Particle and Nuclear Studies
and
M. Fukuda and T. Emura
Tokyo University of Agriculture and Technology

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Radiation tolerance test of 0.3 um CMOS Gate-Array technology was done for neutron and gamma-ray irradiation. The tested technology is a candidate for the TDC chip of the ATLAS precision muon tracker (MDT). In addition to digital circuit, the TDC chip will include a PLL circuit to get a high-resolution less than 1 nsec.
A test element chip (AMT-TEG1) was fabricated. It contains bare NMOS and PMOS transistors, a ring oscillator, a PLL and many other circuit elements used in the TDC.
Gamma-ray irradiation was done by using a Co60 source up to 100 krad(Si) in a worst bias condition. Measurement after annealing (1 week at 100 degree C) was also done. Neutron irradiation is being done at a facility in France. The neutron flux is 1x10**13, 2x10**13 and 4x10**13 n/cm2.  
Variations of transistor parameters and oscillation frequency of the ring oscillator were measured. In addition to the radiation tolerance of the chip, performance of the TDC elements will also be reported. 

!!
Radiation tolerance test of 0.3 um CMOS Gate-Array technology was done for neutron and gamma-ray irradiation. The tested technology is a candidate for the TDC chip of the ATLAS precision muon tracker (MDT). 
A test element chip (AMT-TEG1) contains bare NMOS and PMOS transistors, a ring oscillator, a PLL and many other circuit elements used in the TDC. 
Gamma-ray irradiation was done by using Co60 source in a worst bias condition. Neutron irradiation is being done at a facility in France. 
In addition to the radiation tolerance of the chip, performance of the TDC elements will also be reported. 

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