Kaplon!!Jan!!jan.kaplon@cern.ch!!CERN!!CERN/EP/MIC!!CH 1211!!Geneva 23!!Switzerland!!ATLAS!!TRIG!!Trigger electronics!!Wafer Screening of the Front-End ASICS for ATLAS SCT!!990614000

Jan Kaplon, CERN; Carlos Lacasta Inst. de Fisica Corpuscular (IFIC) Avda. Dr. Moliner, 50 E-46100 Burjassot (Valencia) Espanya 
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The ABCD2T chips will be assembled on the hybrids as unpacked devices and, in consequence, the chip preselection and characterisation process has to be carried out at the level of wafer screening. The characterization process needs to be complete, accurate and as fast as possible since about 50000 chips need to be preselected. Because the ABCD2T chip follows the binary architecture, a considerable amount of measurements are needed to obtain some information on the analogue performance of the front-end. Also a complete set of digital tests checking the readout protocol, different modes of operation and functionality of whole logic need to be desined and carried out. A system fulfilling those requirements has been developed at CERN. The whole process can be divided in three different steps: ï Wafer screening: the whole set of tests are performed on the chip. That comprises testing all the chip functionalities: analogue performance, digital functionality, characterisation of on-chip Digital-to-Analogue Converters, as well as control of the power consumption of the chip. 
ï Data analysis: this part consists on analyzing the data stored during the wafer screening in order to tag the chips according to their performance. 
ï Chip data base maintenance: all the results affecting every single chip should be stored in order to effectively control the shipping process to the institutes in which the modules are to be mounted and follow easily all the test performed on a given chip during and after wafer screening. 
The system is based on a Karl Suss PA200-II probe station with fully motorised chuck stage. The prober can be accessed through GPIB and all the movements are programmed and controlled by software. The custom designed probe card is made with standard technology with 64 needles and a typical pitch of 200um. All signals delivered to and received from the chip are buffered and terminated on the PCB in close distance to the needles. The chip control and the acquisition are driven with two VME modules: the SEQSI, a sequence generator to generate the chip commands, and the DRAFT, to distribute the signals and store the chip data. The basic analogue parameters of the chip,i.e., gain, noise and offset spread are obtained from discriminator threshold scans for various input charges. The chips are operated under nominal conditions for the front-end bias and with the nominal clock frequency of 40 MHz. In what concerns the digital part of the chip, especial emphasis is put in testing all the communication protocol with the chip and among the chips in a hybrid. All the digital test are made varying the chip clock frequency and the digital voltage (Vdd) in order to estimate the speed margins of the digital part. The trigger frequency for data acquisition is, on average, of the order of 4 kHz (acquired data rate about 1Mbit/s). The whole sequence of tests takes about 3.5 minutes per chip. 
The data from the threshold scans, digital test, DAC scans and power consumption are compressed into a file which is analyzed on a separate machine in which a kind of DST for whole wafer is produced with more elaborated information. At this level, from the DST data, a relational database is fed with all the information about position in the wafer, analogue front-end parameters, digital performance, dead channels, DAC linearity, etc, concerning every single chip. 
The system has been successfully working during the last year testing the about 6000 ABCD chips built so far. For the new batch of ABCD2T chips the system has been upgraded to cope with the new functionalities of the chip and the test of the digital part has been extended to study the speed margins. 

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The continuous increase in volume of silicon trackers in the coming experiments poses a number of new issues to unravel. Among them, the high number of detector readout modules to be built in a relatively quick time will require the use of preselected ASICs. In the particular case of the ATLAS SCT, where about 6 million channels have to be read out with little chance of replacement of the electronics, that becomes a considerable challenge. Specific architecture features (amplifier/comparator, pipeline, derandomiser, read-out logic, different services, particular readout protocol) of the front-end chips will call for very specific and especially developed electronic testers to provide a full and efficient characterization. This paper describes the system built for the preselection and characterization of the ABCD2T front-end chips to be used in the readout of the ATLAS SCT microstrip silicon sensors. The system has been used successfully during the last year to tag the 6000 ABCD chips that have been built up to now and has been upgraded to cope with the new features of the last version of the chip. 
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